A Polynomial Multiplication Accelerator for Faster Lattice Cipher Algorithm in Security Chip

Polynomial multiplication is the most computationally expensive part of lattice-based cryptography algorithm. However, existing acceleration schemes have problems, such as low performance and high hardware resource overhead. Based on polynomial number theoretic transformation (NTT), this paper proposed a simple element Montgomery module reduction with pipeline structure to realize fast multiplication. In order improve throughput NTT module, block storage technology used in enable computing unit read write data alternately. precalculated parameter real-time calculation method suitable for architecture also proposed. Finally, multiplier based implemented, its function simulation evaluation are carried out. The results show that accelerator can excellent while using fewer resources, thus meeting requirements lattice cipher algorithms security chips. Compared studies, designed improved by approximately 1 3 times, slice resources reduced 60% 17%, respectively.